Cheng-Hsiang Chiu

Ph.D. student, Department of ECE
University of Wisconsin-Madison, Madison, WI, USA
Office: 3605 Engineering Hall
BS (CCU-EE), MS (NCTU-CM & EPFL-Informatique)           


I am a Ph.D. student in the Department of ECE at the University of Wisconsin-Madison, working on an open-source library, Taskflow, and advised by Prof. Tsung-Wei Huang. My current research focuses on high performance, parallel and heterogeneous computing. I used to investigated in varius projects including edge computing, data analysis, privacy protection and streaming system. During my leisure time, I enjoy playing badminton.

Recent Update

Attendance @ DAC Young Fellows Program 2023

I will attend DAC Young Fellows Program 2023. The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems.

Last updated on 2023/04/18

Received HPDC'22 Student Travel Awards

I received a HPDC'22 Student Travel Awards funded by NSF.

Last updated on 2022/08/08

Software Intern @ intel

My 2022 summer internship in intel is working on oneAPI and SYCL

Last updated on 2022/06/06

Poster Accepted @ HPDC 2022

My paper "Composing Pipeline Parallelism using Control Taskflow Graph" is accepted by HPDC 2022.

Last updated on 2022/04/21

Paper Accepted @ DAC 2022

My paper "Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms" is accepted by DAC 2022.

Last updated on 2022/04/05

Reviewer @ DAC 2022

I reviewed papers of DAC2022.

Last updated on 2022/01/25

Attendance @ DAC Young Fellows Program 2021

I attended DAC Young Fellows Program 2021. The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems.

Last updated on 2021/11/15

Attendance @ CPP Conference 2021

I attended CPP Conference 2021 on October 24-29 in Aurora, Colorado

Last updated on 2021/09/30

Attendance @ ERUO PAR 2021

I gave a presentation of my publication at AMTE, held in conjunction with Euro-par 2021. The title of the publication is "An Experimental Study of SYCL Task Graph Paralleliem for Large-Scale machine Learning Workloads"

Last updated on 2021/09/30

Attendance @ ISPD 2021 Contest

I attended the contest which aims to map a 3-D Finite Element model on a 20D grid of processing elements in a supercomputer, Cerebras CS-1.

Last updated on 2021/03/26

Attendance @ ICCAD 2020

I attended the tutorial session talking about experience of using Taskflow to parallelize CADGPU Acceleration in CAD: Opportunities and Challenges at the 2020 IEEE/ACM International Conference on Computer-aided Design (ICCAD)!

Last updated on 2021/03/26

Attendance @ WOSET 2020

I attended the presentation of Taskflow at the 2020 Workshop of Open-source EDA Technology (WOSET) co-located with the International Conference on Computer-aided Design (ICCAD)!

Last updated on 2021/03/26

Attendance @ MUC++ 2020

I attended the event presenting to the C++ group at München, Germany. Taskflow: A General-purpose Parallel and Heterogeneous Task Programming System, on Thu, Oct 22, 7:00 PM GMT+2.

Last updated on 2021/03/26

Attendance @ CppCon 2020

I attended CppCon 2020 and listened to many marvelous talks!

Last updated on 2020/10/21

Attendance @ HPEC 2020

I attended IEEE HPEC 2020.

Last updated on 2020/10/21

Current Project

Taskflow, AsyncTask, Pipeflow, syclFlow

Taskflow helps C++ developers quickly and efficiently write parallel and heterogeneous programs with high performance and simultaneous high productivity. AsyncTask allows users to explore dynamic task graph parallelism in their applications. Pipeflow provides an efficient pipeline scheduling framework. syclFLow allows users to write GPU codes using single source programming model SYCL easily.

Past Projects

VLSI floor planner

A floor planner that maps a 3-D physical finite element model onto a 2-D grid of processing units in a supercomputer.

Energy efficient edge computing in Arctic

Energy efficient edge computing devices reduce power consumption of wildlife classification platform in Arctic tundra.

Data visualization and analysis

Parallel simulations calculate power data, two-dimension materials and soil classification and present analysis with suitable visualizations.

Privacy protection

Technique prevents malicious Apps from profiling users' privacy.

Movie Recommender via Amazon Mechanical Turk

Method alleviates cold start problem in recommender systems.

Vision-based intelligent environment

vision-based security surveillance aims to an intelligent living environment.


Conference Papers

  1. Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, and Tsung-Wei Huang, "HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2025
  2. Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, "iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2025
  3. Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, "PathGen: An Efficient Parallel Critical Path Generation Algorithm," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2025
  4. Cheng-Hsiang Chiu, Chedi Morchdi, Yi Zhou, Boyang Zhang, Che Chang, and Tsung-Wei Huang, "Reinforcement Learning-generated Topological Order for Dynamic Task Graph Scheduling", IEEE High-performance and Extreme Computing Conference (HPEC), 2024
  5. Cheng-Hsiang Chiu and Tsung-Wei Huang, "An Experimental Study of Dynamic Task Graph Parallelishm for Large-Scale Circuit Analysis Workloads", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2024
  6. Che Chang, Cheng-Hsiang Chiu, Boyang Zhang, and Tsung-Wei Huang, "Incremental Critical Path Generation for Dynamic Graphs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2024
  7. Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan Luan Lee, Chih-Chun Chang, Donghao Fang, and Tsung-Wei Huang, "G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis," ACM/IEEE Design Automation Conference (DAC), 2024
  8. Tsung-Wei Huang, Boyang Zhang, Dian-Lun Lin, and Cheng-Hsiang Chiu, "Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System," ACM International Symposium on Physical Design (ISPD), 2024
  9. Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, and Yibo Lin, "An Efficient Task-parallel Pipeline Programming Framework," ACM International Conference on High-performance Computing in Asia-Pacific Region (HPC Asia), 2024.
  10. Chedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou, and Tsung-Wei Huang, " A Resource-efficient Task Scheduling System using Reinforcement Learning," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
  11. Cheng-Hsiang Chiu, Dian-Lun Lin, and Tsung-Wei Huang, "Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms," IEEE/ACM International Conference on Computer-aided Design (ICCAD), 2023.
  12. Cheng-Hsiang Chiu and Tsung-Wei Huang, "Composing Pipeline Parallelism using Control Taskflow Graph," ACM High-Performance Parallel and Distributed Computing (HPDC), 2022.
  13. Cheng-Hsiang Chiu and Tsung-Wei Huang, "Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms," Design Automation Conference (DAC), 2022.
  14. Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, and Yibo Lin, "Pipeflow: An Efficient Task- Parallel Pipeline Programming Framework using Modern C++," Arxiv, 2022.
  15. Cheng-Hsiang Chiu, Dian-Lun Lin, and Tsung-Wei Huang, "An Experimental Study of SYCL Task Graph Parallelism for Large-Scale Machine Learning Workloads," International European Conference on Parallel and Distributed Computing (EURO-PAR), 2021.
  16. Der-Cherng Liaw, Jing-Hong Lai, Cheng-Hsiang Chiu, and Jia-Hong Liao, "A Wireless Sensor Network Platform for Indoor Surveillance System," International Conference on System Science and Engineering, 2011.
  17. Der-Cherng Liaw, Yi-Hung Hsieh, Jing-Hong Lai, and Cheng-Hsiang Chiu, "A Network Topology Design for Structural Health Monitoring," Asian Control Conference, 2011.
  18. Der-Cherng Liaw, Chia-Wei Yeh, Cheng-Hsiang Chiu, Chia-Ming Chang, and Hsiao-Jen Hsieh, "A Load Balancing Scheme for Web Server Design," International Conference on System Science and Engineering, 2011.
  19. Der-Cherng Liaw, Cheng-Hsiang Chiu, Chia-Wei Yeh, Chia-Ming Chang, and Hsiao-Jen Hsieh, "A Server Load Balancing Design for Peer-To-Peer Network," International Conference on Mechanical Engineering and Technology, 2011.
  20. Cheng-Hsiang Chiu, Pang-Chan Hung, Jen-Hui Chuang, and Shing-Lu Huang, "Object Tracking under Sensing Lighting Equipments," IEEE Conference on Industrial Electronics and Applications, 2010.
  21. Yi-Yuan Chen, Yuan-Yao Tu, Cheng-Hsiang Chiu, and Yong-Sheng Chen, "An Embedded System for Vehicle Surrounding Monitoring," IEEE Conference on Power Electronics and Intelligent Transportation System, 2009.

Journal Papers

  1. Yu-Cheng Chiou, Tuza Adeyemi Olukan, Mariam Ali Almahri, Harry Apostoleris, Cheng- Hsiang Chiu, Chia-Yun Lai, Jin-You Lu, Sergio Santos, Ibraheem Almansouri, and Matteo Chiesa, "Direct Measurement of the Magnitude of van der Waals interaction of Single and Multilayer Graphene," ACS LANGUMIR, 2018

Semester Project Reports

  1. Cheng-Hsiang Chiu, "Bootstrapping recommender systems with the crowdsourcing II," École Polytechnique Fédérale de Lausanne, 2015
  2. Cheng-Hsiang Chiu, "Bootstrapping recommender systems with the crowdsourcing," École Polytechnique Fédérale de Lausanne, 2014

Thesis

  1. Cheng-Hsiang Chiu, "Protection against Data Profiling by Adversarial Cloud Applications," Master Thesis, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 2016
  2. Cheng-Hsiang Chiu, "Process control in Streaming Server," Master Thesis, National Chiao Tung University, Taiwan, 2007